Module


General information
FPGA Prototyping by VHDL examples
FPGA Prototyping by VHDL examples
MK114
Prof. Dr. Jetzek, Ulrich (ulrich.jetzek@haw-kiel.de)
Prof. Dr. Jetzek, Ulrich (ulrich.jetzek@haw-kiel.de)
Rohrandt, Christian (christian.rohrandt@haw-kiel.de)
Sommersemester 2019
1 Semester
In der Regel im Sommersemester
Englisch
Curricular relevance (according to examination regulations)
Study Subject Study Specialization Study Focus Module type Semester
M.Eng. - MET - Elektrische Technologien (PO 2017, V3) Kommunikationstechnik und Embedded Systems Wahlmodul
M.Sc. - MIE - Information Engineering (PO 2022, V3) IT Security Wahlmodul
M.Sc. - MIE - Information Engineering (PO 2022, V3) Information Technology and Systems Wahlmodul
M.Eng. - MET - Elektrische Technologien (PO 2017, V3) Elektrische Energietechnik Wahlmodul
M.Sc. - MIE - Information Engineering (PO 2022, V3) Intelligent Systems Wahlmodul
M.Eng. - MET - Elektrische Technologien (PO 2017, V3) Mechatronik Wahlmodul

Qualification outcome
Areas of Competence: Knowledge and Understanding; Use, application and generation of knowledge; Communication and cooperation; Scientific self-understanding / professionalism.
The students have understood the fundamentals of the Hardware Description Language VHDL. They know the principle how to design combinatorial as well as sequential circuits and how to implement a finite state machine in VHDL. They are able to apply this knowledge to design regular sequential circuits like Counters or shift Registers as well as circuits for finite state machines. The students know how to partition a System into control and data plane and how to implement the corresponding circuits in VHDL.They know how to set up a testbench and are capable of simulating VHDL designs as well as how to set up simple testing circuits to a specific VHDL design on a development board.
Within the lab exercises, the students have the possibility to apply their knowledge by implementing given problems on a development board and to validate their implementation approach.
The students work together in small teams in the lab. Therefore they are capable of structuring lab exercises into different work packages, to discuss and solve problems, which occur throughout the implementation process, within the team and they are able to document their lab exercise results in a systematic and structured way.
Content information
- synthesis of combinational digital circuits
- structured VHDL coding
- design of digital functions using the VHDL concept of ‚processes’
- design and verification of sequential circuits
- design and verification of finite state machines
- control and usage of common technical components like UART, FIFO or VGA (graphics).
The different topics will be implemented on the ZED-Board, which is a powerful Xilinx development board equipped with a Zynq System-on-Chip (SoC).
- Jürgen Reichardt, Bernd Schwarz: „VHDL Synthese – Entwurf digitaler Schaltungen und Systeme“, Oldenbourg Verl., 5.Aufl., 2009
- Pong P. Chu: “FPGA Prototyping by VHDL-Examples”, Wiley & Sons, 2008
Teaching formats of the courses
Teaching format SWS
Labor 2
Lehrvortrag 2
Workload
4 SWS
5,0 Credits
48 Hours
102 Hours
Module Examination
Method of Examination Duration Weighting wird angerechnet gem. § 11 Absatz 2 PVO Graded Remark
Klausur 90 Minutes 100 %
Übung 0 %